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Question: Enable bit plays an important role in decoder expansions. How is this justified in designing 5X32 line decoder using 2×4 decoders – Free Chegg Question Answer

Enable bit plays an important role in decoder expansions. How is this justified in designing 5X32 line decoder using 2×4 decoders

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The answer as follows :

A decoder is a combinational circuit that takes n binary inputs and maps them to 2n number outputs. In a 2 × 4 decoder there are 2 (two) inputs and 4 (four) outputs, whereas in a 5 × 32 line decoder there are 5 (five) inputs and 32 (thirty two) outputs where only one is high (enable). So a 5-input decoder there are 25 i.e. 32 outputs. It can be implemented by decoding logic by stages of smaller decoders as well. So, to implement 5 × 32 line decoders, 4 (four) numbers of 3-to-8 (3 × 8) line decoders can be taken to get 32 outputs and each of the four decoders can then be selected through a single 2-to-4 (2 × 4) line decoder.

It can be implemented in two (stages). Inititially two 2×4 decoders are required for implementing one 3 × 8 decoder in the first (1st) stage.

The block diagram of 3 × 8 decoder using 2×4 decoders is shown in the following figure:

Y7 2 to 4 Decoder Y6 Y5 Y4 НЕ Y3 A1 2 to 4 Decoder Y2 Ао Y1 YO E

The parallel inputs A1 & A0 are applied to each 2×4 decoder. The complement of input A2 is connected to Enable, E of lower 2 to 4 decoder in order to get the outputs, Y3 to Y0. These are the lower four min terms. The input, A2 is directly connected to Enable, E of upper 2 to 4 decoder in order to get the outputs, Y7 to Y4. These are the higher four min terms. Thus 2 (two) numbers of 2×4 decoders are required to construct each 3 × 8 line decoder.

Now to implement 5×32 line decoder as shown below:   

D31 D30 14 13 12 11 10 5-to-32 Decoder D1 DO En

Number of inputs (5) : I0 to I4

Enable bit : En

Number of outputs (32) : D0 to D31

In the second (2nd) stage one (01) number of 2×4 line decoder is required with four (04) numbers of 3 × 8 line decoders for selecting each of them, as follows :

12 3-to-8 Decoder DT Пн DS nu D3 D2 DI DO D31 DSO 025 028 D27 D26 D25 24 10 10 En 3-to-8 Decoder DT 05 DS 04 D3 D2 DI DO 023

Fig. 1 : 5 × 32 line decoder using 2 × 4 decoders

I0, I1 and I2 are the inputs of 3 × 8 decoders, whereas I3 and I4 are the inputs of 2×4 decoders.

En is the enable bit of all the decoders. So, there are 5 (five) number of inputs. Each 3 × 8 decoder has 8 (eight) number of outputs as shown in Fig. 1. Hence, there are 32 (thirty two) number of ouputs from the above 5 number of inputs.

Therefore, the above Fig.1 thus justified in designing 5 × 32 line decoder using 2 × 4 decoders.


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